//------------------------------------------------------------
//  Filename: version_ctrl.v
//   
//  Author  : wlduan@gmail.com
//  Revise  : 2017-08-18 19:26
//  Description: 
//   
//  Copyright (C) 2014, YRBD, Inc. 					      
//  All Rights Reserved.                                       
//-------------------------------------------------------------
//
`timescale 1ns/1ps

module VERSION_CTRL ( 

    input  wire        clka  ,
    input  wire [15:0] addra ,
    output wire [23:0] douta ,
 
    input  wire        clkb  ,
    input  wire [15:0] addrb ,
    output wire [23:0] doutb ,

    output wire [31:0] hardware_version 
);      
//--------------------------------------------------------
wire[7:0] main_v = 3;
//--------------------------------------------------------
assign hardware_version = {8'b0,main_v,8'd1,8'd2}; // FUSION_V1
//-------------------------------------------------------- 
rom24x512_Initcfg_vector init_rom(
    .clka  ( clka  ),
    .addra ( addra[9:0] ),
    .douta ( douta ),
                   
    .clkb  ( clkb  ),
    .addrb ( addrb[9:0] ),
    .doutb ( doutb )
);

endmodule
